The present invention relates to a semiconductor device and more specifically to an improved contact structure of conductor lines which lie on a rough surface of a semiconductor substrate.
In the production of a semiconductor device (e.g. IC, LSI), generally, a variety of thin layers, such as silicon dioxide (SiO.sub.2), polycrystalline silicon, silicon nitride (Si.sub.3 N.sub.4) and phosphosilicate glass (PSG), are used and each of the thin layers is selectively etched to form a hole (i.e. an opening) and then a conductor line of metal is formed on a thin layer so as to traverse the hole. In such a case, a side wall of the hole is sometimes located on a step or slope of a surface portion of a semiconductor substrate or an insulating layer which lies under the thin layer. Especially in the case where a higher density semiconductor device is produced, a side wall of the hole is often located on the step or slope.
For example, a thin silicon dioxide layer 1 and a thick silicon dioxide layer 2 are formed on a semiconductor substrate 3 having a step-like portion, as illustrated in FIG. 1. In order to selectively etch the thin silicon dioxide layer 1 so as to form a hole for the succeeding processing wherein a region 4 having diffused impurities of the substrate 3 is exposed, a photoresist layer 5 (FIG. 1) is formed on the thick silicon dioxide layer 2 so as to cover the upper portion of the slope of the layer 2 above the step-like portion. When etching is carried out, the thin silicon dioxide layer is removed, and, simultaneously, a side portion of the thick silicon dioxide layer 2 is removed, thereby creating a so-called overhang A, as illustrated in FIG. 2. Then a conductor line 6 comprised of metal such as aluminum is formed by means of a vacuum deposition method. However, a defect, i.e. a crack (illustrated in FIG. 2), is present in the conductor line 6 at the overhang so that the coverage of the conductor line 6 at the side of the thick silicon dioxide layer 2 (i.e. a so-called step coverage) is not good. Whether or not the conductor line 6 will break depends on the circumstances. Since an etching solution can easily enter the crack and since the conductor line 6 at the overhang is remarkably thin, the life and reliability of the semiconductor device is decreased.
In another case, a thin layer 11 of polycrystalline silicon is formed on an insulating layer 12 of silicon dioxide having a step-like portion and lies on a semiconductor substrate 13 (FIG. 3). In this case, the polycrystalline silicon layer 11 is deposited with uniform thickness by using a well-known low pressure chemical vapor deposition method. The polycrystalline silicon layer is used as the underlying layer for an aluminum conductor layer. In order to selectively remove a portion of the polycrystalline layer 11 so as to form a hole by means of a photoetching method, the other portion of the layer 11 is covered with a photoresist layer 14, as illustrated in FIG. 3. The end of the photoresist layer 14 covers the upper portion of the slope of the polycrystalline silicon layer 11. When etching is carried out, the exposed portion of the polycrystalline silicon layer 11 is removed so that a side of the hole is located on the slope of the step-like portion of the silicon dioxide layer 12, as illustrated in FIG. 4. As a result of etching, an overhang B (FIG. 4) is created on the upper part of the slope. Then a conductor line 15 (FIG. 4) of metal is formed on the polycrystalline silicon layer 11 and on the exposed thin portion of the silicon dioxide layer 12 so as to traverse the side of the hole. In this case, a defect similar to that in FIG. 2 is present in the conductor line 15 at the overhang B. In order to prevent a defect in the conductor line 15 it can be considered that the hole of the polycrystalline silicon layer 11 should be made larger so as to locate a side 16 of the larger hole away from the edge 17 of the slope of the step-like portion, as illustrated in FIGS. 5 and 6. However, since the registration tolerance must be taken into consideration, the distance L from the edge 17 of the slope of the step-like portion to the side 16 of the hole may be the sum of a predetermined distance and the maximum tolerance. In such a case, the dimensions of the hole can become too large, thereby preventing an increase in the density of the semiconductor device. In particular, when a multilayer structure is made of three or more layers, the arrangement of holes formed in different layers must be taken into consideration so that the registration tolerance can be increased. As a result, the dimensions of the holes may be increased further.